Principal DFT Engineer

Position Type - Full Time Job role with benefits like RSUs , Bonus etc

Job Location - San Jose-CA

Job Description -

We are seeking an experienced Principal DFT Engineer to lead design-for-test implementation and verification for complex SoC designs. The ideal candidate will have deep hands-on expertise with Siemens Tessent tools, hierarchical DFT flows, scan compression, MBIST, LBIST, and silicon debug.

• Own and drive end-to-end DFT architecture, implementation, verification, and test-pattern release for complex SoCs.
• Develop and maintain Tessent-based DFT flows, including Tessent Shell and Tessent LV flows.
• Implement scan insertion, scan compression, ATPG, test-point insertion, boundary scan, and at-speed test.
• Define and implement hierarchical and bottom-up DFT strategies, including wrapper-chain and graybox generation.
• Plan and optimize scan architecture, pin allocation, test modes, and compression ratios across multiple partitions.
• Implement and verify MBIST solutions, including controller assignment and memory testing across multiple power domains.
• Support or implement LBIST/LogicBIST methodologies where applicable.
• Address DFT requirements for multiple power domains, including isolation, power-aware test controls, and power-domain-aware test architecture.
• Generate and review DFT deliverables, including DFT rule-check reports, coverage reports, ATPG patterns, simulation results, test protocols, and ATE collateral.
• Debug scan, ATPG, MBIST, and at-speed pattern simulation failures.
• Work closely with design, verification, physical design, STA, firmware, product engineering, and ATE teams.
• Support bring-up, diagnosis, and debug of scan and MBIST failures on silicon and ATE.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of hands-on DFT experience for ASIC or SoC designs.
• Strong expertise with Siemens Tessent tools, including Tessent Shell and Tessent LV.
• Proven experience with scan insertion, ATPG, compression, MBIST, boundary scan, and at-speed scan testing.
• Strong understanding of hierarchical DFT, wrapper chains, graybox models, and bottom-up implementation flows.
• Experience with multi-power-domain DFT architecture and power-aware test implementation.
• Experience debugging DFT simulations and resolving scan or MBIST test failures.
• Knowledge of timing constraints, including false paths and multicycle paths, for at-speed ATPG and pattern simulation.
• Experience preparing patterns and collateral for ATE bring-up, test execution, diagnosis, and yield debug.
• Strong scripting skills in Tcl, Perl, Python, or shell scripting.

• Experience with LBIST/LogicBIST implementation and verification.
• Experience with silicon bring-up, scan diagnosis, and yield analysis.
• Familiarity with memory repair, BISR, and advanced DFT methodologies.
• Experience leading DFT execution across multiple blocks, teams, or product programs.

The successful candidate will independently lead DFT execution from architecture through silicon debug, deliver high-quality test collateral on schedule, achieve strong test coverage, and help resolve complex manufacturing and bring-up issues.