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Senior ATE Test Engineer – SoC Speed Protocols
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-09-05
Listing for:
Asteralabs
Full Time
position Listed on 2026-09-05
Job specializations:
-
Engineering
Test Engineer, Electronics Engineer
Job Description & How to Apply Below
Astra Labs is seeking a Senior ATE Test Engineer to lead SoC test strategies for high-volume mixed-signal silicon products. You will define ATE programs, work with manufacturing partners, and own the product from design to ramp.
You should have 2+ years releasing SoC silicon to high-volume manufacturing, hands-on experience with PCIe/Ethernet/Infiniband/DDR/NVMe/USB, and strong programming skills in C/C++ or Python. Remote options not specified.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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