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Principal SerDes/PHY Verification Architect AI Infra
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-09-05
Listing for:
Asteralabs
Full Time
position Listed on 2026-09-05
Job specializations:
-
Engineering
Test Engineer, Hardware Engineer
Job Description & How to Apply Below
Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed Ser Des/PHY IP, the connectivity engine behind next‑gen AI platforms. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success across the analog/digital boundary.
You will partner with PHY analog/mixed‑signal designers and SoC teams to verify Ser Des blocks that ship into PCIe Gen6/Gen7, UALink, UCIe, and Ethernet products.
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