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Senior Physical Design Engineer - RTL-to-GDS Tapeout
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-09-07
Listing for:
TSMC - Taiwan Semiconductor Manufacturing Company Limited
Full Time
position Listed on 2026-09-07
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
TSMC in San Jose seeks a Physical Design Engineer to own RTL-to-GDS flow, from synthesis to signoff, including CTS, STA, and P&R. You will report to the Senior Manager at the San Jose Center as part of a team driving advanced semiconductor manufacturing excellence.
The role requires mastering block-level implementation, floor planning analysis, ECO timing fixes, and thorough physical verification, with a hybrid work schedule (4 days in office). Prior experience with TSMC N16 or below is preferred.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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