Analog Layout Engineer

Job Description

Job Description

We are seeking an experienced Analog Layout Engineer to support the development and implementation of custom analog and high-speed circuit blocks. The ideal candidate will have strong hands-on experience with analog IC layout, advanced process technologies, physical verification, and layout optimization.

Responsibilities

• Perform layout of analog and high-speed transceiver circuit blocks, including amplifiers, drivers, ADCs, DACs, LDOs, PLLs, filters, and related circuits.
• Develop layouts for sensitive active and passive components, including resistors, capacitors, and inductors.
• Perform design verification, including DRC, LVS, ERC, ANT , and parasitic extraction.
• Collaborate with circuit and design engineers on block-level floor planning.
• Review and update layouts to optimize signal integrity, power integrity, matching, and parasitic performance.
• Analyze and address layout-related issues involving coupling, parasitics, area, matching, ESD, and latch-up.
• Interpret physical verification results and implement corrective actions as needed.
• Work closely with cross-functional engineering teams to deliver high-quality layouts within project schedules.

Basic Qualifications

• Associate degree or higher with formal training in custom analog layout.
• Bachelor's degree in Electrical Engineering or a related field is preferred.
• 5+ years of experience in analog layout, preferably in deep sub-micron and FinFET process technologies.

Preferred Qualifications

• Strong experience with floor planning and layout of analog circuit blocks, including amplifiers, drivers, ADCs, DACs, LDOs, PLLs, filters, and high-speed transceiver circuits.
• Solid understanding of semiconductor device structures and custom analog layout techniques.
• Strong understanding of layout tradeoffs involving matching, coupling, parasitic effects, area, and performance.
• Knowledge of ESD and latch-up mechanisms, including prevention techniques.
• Proficiency in interpreting and resolving DRC, LVS, ERC, and ANT verification results.
• Experience with parasitic extraction and post-layout considerations.
• Working knowledge of Cadence Virtuoso and Mentor Calibre is required.