ASIC Design Engineer

• Opportunity to work on cutting-edge AI-SSD architecture
• High-impact role in next-generation storage innovation
• Collaborative and fast-paced engineering culture

Responsibilities

1.Contribute to the microarchitecture design of next-generation SSD controllers and storage subsystems, with a focus on optimizing architectures for AI applications.

2.Develop and write detailed design specifications, microarchitecture documents, and implementation guidelines.

3.Design and implement key functional blocks using Verilog/System Verilog RTL.

4.Work closely with the verification team to define test plans, coverage analysis, and support full-chip simulation, debug, and validation.

5.Collaborate with the physical design team to ensure timely and high-quality RTL-to-GDS implementation.

6.Support post-silicon bring-up, debugging, and performance validation in the lab.

7.Work closely with firmware and system teams to ensure feature alignment and product-level performance targets are met.

8.Perform design analysis and optimization to improve performance, power efficiency, and area (PPA).

Qualifications

1.Bachelor’s degree or above in Electrical Engineering, Computer Engineering, Computer Science, or related fields.

2.3+ years of ASIC design experience, preferably in storage or high-performance SoC design.

3.Strong understanding of the full ASIC design flow, including both front-end and back-end processes.

4.Solid experience in digital design and RTL development, with proficiency in Verilog/System Verilog.

5.Familiarity with at least one scripting/programming language (e.g., Python, Tcl, Perl, Shell).

6.Strong problem-solving skills, self-motivated, and able to work effectively in a collaborative team environment.

Preferred Qualifications

1.Experience in SSD controller or storage system design

2.Familiarity with AI/ML workload acceleration, memory/storage hierarchy, high throughput DMA, FIFO design or data path optimization.

3.Hands-on experience with synthesis (Design Compiler), STA, CDC, lint, and formal verification flows.

4.Knowledge of UVM-based verification methodologies.