Sr. Hardware Engineer; EDVT & PHY Qual

The application window is expected to close on: 10/13/2026

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. As a Senior Hardware Validation Engineer, you will lead the electrical design validation and physical layer (PHY) qualification for our next-generation enterprise and industrial switches.

You will be responsible for ensuring our hardware meets the highest quality, performance, and industry standards.

As a Sr. Hardware Engineer, you will drive product excellence by designing and executing comprehensive, end-to-end test architectures across complex board components and PHY systems. Leveraging test automation, scripting, and cross-functional collaboration, you will debug root-cause issues and ensure seamless compliance with industry standards for successful mass production releases. Beyond technical execution, you will act as a key technical leader—owning critical projects, mentoring junior engineers, and establishing standard test frameworks that scale product quality across the organization.

• Bachelor’s degree in Electrical or Computer Engineering (7+ years of experience) or MSEE/CE (5+ years of experience).

• Prior experience in the field of networking hardware validation/testing.

• Prior hands‑on experience with electrical and optical test equipment (Oscilloscopes, Power meters, Signal generators, VNA (Vector Network Analyzers), and Thermal chambers).

• Prior experience with L2/L3 routing and switching, OSI Model, and LAN/WAN topologies.

• Prior experience with Python for test automation.

• Prior experience with high-speed interfaces, including 10G/25G/100G/400G network interfaces.

• Prior experience with PHY/Signal Integrity for high-pass/low-pass filters, and IEEE 802.3 signal compliance testing.

• Prior experience with Power/Bus architecture, including prior knowledge of Power over Ethernet (PoE) testing, CPU, clocking, and bus architectures (PCIe, USB, I2C).

• Prior experience with traffic generators such as Ixia or Spirent.

• Prior experience with EMI/EMC testing and regulatory compliance.

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

The starting salary range posted for this position is $ to $ and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short…