Senior FPGA Circuit Design Engineer

About Altera

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

Join Altera as a Senior FPGA Silicon Design Engineer focused on the design and development of complex FPGA circuits, programmable logic, and IP for next‑generation FPGA products.

In this role, you will own significant portions of FPGA architecture and implementation, including core fabric logic, interconnect and routing, clocking, configuration, configurable memory blocks, and Network-on-Chip (NoC) capabilities. You will apply deep expertise in FPGA and/or ASIC design to micro‑architect, design, simulate, and verify complex circuits and logic while optimizing designs for power, performance, area, timing, reliability, and yield. You will also develop the models, specifications, and design collateral required to integrate FPGA circuits and IP into broader hardware and software deliverables.

As a senior technical contributor, you will work closely with microarchitecture, SoC/full‑chip, IP fabric and interconnect, RTL design, verification, physical design, and other engineering teams to develop new FPGA capabilities, improve programmable logic architectures, and enable efficient integration of FPGA technology into larger systems.

You will independently drive complex technical assignments, influence design decisions, mentor engineers, and contribute to improved design methodologies and processes.

• Design and develop complex FPGA circuits and IP, including FPGA core fabric logic, interconnect and routing, clocking, configuration, configurable memory blocks, and Network‑on‑Chip (NoC) architectures.
• Lead microarchitecture definition and perform circuit and logic design for complex FPGA blocks and subsystems, making technical tradeoffs to optimize power, performance, area, timing, reliability, and yield.
• Develop schematics, RTL implementations, behavioral models, and simulations to evaluate and validate new FPGA circuit architectures and capabilities.
• Perform functional and reliability verification of FPGA circuits and IP, working closely with verification teams to identify, debug, and resolve complex design issues.
• Develop and maintain design models and collateral required to integrate FPGA circuits and IP into hardware and software deliverables, including circuit integration specifications, behavioral models, electrical rule checkers, design intent, timing models, and power models.
• Analyze design results and drive improvements to meet aggressive power, performance, area (PPA), timing, reliability, and yield objectives.
• Work closely with microarchitecture, SoC/full‑chip, IP fabric and interconnect, RTL design, verification, physical design, and other cross‑functional teams to integrate FPGA circuits and IP into larger systems.
• Drive technical resolution of complex design, integration, simulation, timing, and functional issues across multiple engineering disciplines.
• Contribute to the development of new FPGA capabilities and improved programmable logic architectures that enable faster and more efficient integration of Altera FPGAs into larger systems.
• Lead or contribute to design methodology and flow improvements that increase design quality, development efficiency, and scalability across FPGA product generations.
• Provide technical guidance and mentorship to less‑experienced engineers and serve as a technical resource for complex FPGA circuit and IP design challenges.
• Support silicon bring‑up and post‑silicon debug as needed by investigating hardware issues, validating design functionality, and applying lessons learned to future FPGA designs.

The pay range below is for Bay Area…