Head of Test Development Engineering

Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakthrough data transport and acceleration technology is ushering in a new era of connectivity and capabilities in the vehicle and at the edge, including highly reliable autonomy, over-the-air servicing and AI-backed applications.

Ethernovia's co-founders are serial technology entrepreneurs with multiple prior successful ventures together. We are well-funded and backed by some of the worlds’ leading technology investors, having secured $154M ($90+M Series-B and $64M Series-A) in total funding to date:

• (financial backers include:
  Porsche SE, Qualcomm, AMD, Western Digital, Maverick Silicon, Socratic Partners, Conduit Capital, and CDIB-TEN Capital)

Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025.

With talented employees on 4 continents, we have filed 50+ patents to date.

Join Ethernovia’s team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive cutting edge designs from concept to silicon to the future of mobility.

Head of Test Development Engineering

Summary:

The Head of Product Development Engineering will be responsible for taking Ethernovia’s products from NPI to HVM.

This position requires a leader who is hands-on with semiconductor test development
. You will bridge the gap between world-class networking chip designs and high-volume, automotive-grade silicon testing. The position is based in San Jose, CA.

Key Responsibilities:

• End to end, test architecture, infrastructure, hardware and methodology ownership from pre-silicon to post-silicon
  , working with Arch, Design, Desing verification, DFT, Security, SW/FW, System, Product and Q&R.
• Own early engagement with Arch/DFT, System/SW and Security, on ATE and SLT test architecture and DFM / DFD to ensure debug ability and testability to spec.
• Deliver manufacturing test programs from NPI bring-up to high volume manufacturing for high-speed Ethernet switch and PHY products ensuring signal integrity and power/performance standards are maintained at scale.
• Own design of test boards ensuring SI/PI and test implementation across wafer test, final test and system level test, ensuring robustness and meeting test time.
• Manage test labs, OSAT (test house), engagement with vendors for tester, prober, probe card, load board, system board, socket, handler, change kit and TCU.

Required Experience &

Skills:

• Bachelor's or Master's degree in Electrical Engineeringor a related technical field
• 12+ years of experience in fabless semiconductor operations
  , specifically for complex, high-performance SOCs or networking ICs.
• Expert in ATE 93K platform and Smartest, test method libraries and design of test hardware with robust SI/PI for wafer and final test.
• Expertise with iJTAG, Scan (SSN), MBIST, Sensor, Ser Des, LSIO/HSIO testing
  , security fusing and test automation for multi-site (x8, x16) parallel testing.
• Expert in SLT testing using bare-metal, functional DVFS and benchmark testing and expert in multi-site handler automation framework and test log standards.
• Experience with Analog characterizing high-speed communication chips on ATE and System to ensure all IO parameters are…