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Senior Analog Layout Engineer - Onsite -Perf CMOS ICs
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-09-09
Listing for:
Redolent Infotech Pvt. Ltd.
Full Time
position Listed on 2026-09-09
Job specializations:
-
Engineering
Electronics Engineer
Job Description & How to Apply Below
Redolent Infotech Pvt. Ltd. in San Jose, CA is seeking an experienced Analog Layout Engineer for an onsite, six-month contracting position.
You will lead the layout of high-performance analog cores, including ADCs, DACs and PLLs, across multiple CMOS nodes. The role requires 10+ years of analog layout experience in advanced CMOS processes, strong knowledge of Cadence, Mentor, and Synopsys tools, and proven collaboration with distributed teams.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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