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Lead -Speed Analog Layout Architect
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-09-09
Listing for:
Celero Communications, Inc.
Full Time
position Listed on 2026-09-09
Job specializations:
-
Engineering
Electronics Engineer, Systems Engineer
Job Description & How to Apply Below
Celero Communications, Inc. is seeking a Senior/Principal Analog Layout Engineer to drive the layout of complex IP blocks (ADCs, DACs, PLLs) for high-performance optical communication systems.
You will lead layout development, collaborate with circuit designers, and mentor junior engineers across time zones. The role involves hands-on layout in advanced CMOS/FinFET processes, top-level planning, and verification using industry tools.
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