Senior Electronics Engineer; Digital

Qualifications

• M.S. in Electrical Engineering or Computer Engineering with 3+ years of relevant industry experience, or Ph.D. in a related field.
• Strong proficiency in Verilog or VHDL for RTL development.
• Solid knowledge of embedded Linux systems with strong C programming skills.
• Hands‑on experience with FPGA board‑level design using Intel Quartus, including RTL design, module‑level simulation, timing constraints (SDC), static timing analysis (STA) etc.
• Experience designing and integrating bus protocols, such as Avalon Streaming and Avalon Memory‑Mapped, as well as industry‑standard interfaces including SPI, UART, and Ethernet.
• Experience with DDR3/DDR4 memory controller design and high‑speed Ser Des interface control.
• Strong foundation in digital hardware design, with the ability to read and interpret circuit schematics; analog hardware knowledge is a plus.
• Excellent troubleshooting, analytical, and communication skills, with the ability to work effectively in cross‑functional teams.

• Self‑motivated, have a keen eye to identify bottlenecks/risks and drive improvement.
• Good problem‑solving skill.
• Work smarter, not harder.
• Can learn and apply new information, tools or skills.
• Must be able to read and interpret data, information, and documents.
• Strong customer focus and commitment to customer satisfaction through prioritization, quality, efficiency and professionalism. Ability to complete assignments with attention to detail and high degree of accuracy.
• Proven ability to perform effectively in a demanding environment with changing workloads. Result driven—demonstrate ownership and accountability. Work independently or as part of a team and follow through on assignments with minimal supervision.
• Demonstrate open, clear, concise and professional communication. Ability to establish and maintain cooperative working relationships with co‑workers and customer. Work according to a strict set of procedures within the provided timelines.

EOE AA M/F/Veteran/Disability