Senior Technical Staff Engineer - Validation; System Design

Senior Technical Staff Engineer - Validation (System Design)

Location:

San Jose, CA. This role focuses on lab bring‑up and automation of FPGA design creation and validation, systems‑level design using FPGAs, and development of partial re‑configuration use cases.

• Expertise in using FPGAs to create systems‑level designs, bring up and debug such systems in the lab, including validating systems‑level UCs for partial reconfiguration.
• Architecture definition and FPGA design creation utilizing all hardware features and IP cores targeted to existing and future Microchip products.
• Development of high‑level system and product‑level validation plans for new and existing silicon products, execution per plan, review of dependencies, effort estimation, and risk communication.
• Understanding hardware architectures, defining use models, and executing/overseeing system‑level design implementations required to utilize silicon features.
• Act as the technical expert on protocols using high‑speed serial interfaces in a cross‑functional team‑oriented environment.
• Write high‑quality code in Verilog, VHDL and C; maintain existing code and support regression and re‑use.
• Learn new system designs and validation methodologies; understand FPGA architectures.
• Provide technical guidance, mentor senior and junior engineers, assign and monitor tasks of employees and contractors.
• Collaborate with cross‑functional managers/teams to identify and resolve inter‑dependencies.
• Define and improve processes within the department; follow quality metrics and assess per project.
• Be willing to take regular late‑night or early‑morning calls to interface with the engineering team in India Standard Time zone, when required.
• Use AI‑based tools to automate workflows and improve FPGA design and validation processes.

• BSEE / BSCS or equivalent with 15+ years of experience.
• MSEE / MSCS preferred.
• Knowledge of FPGA architectures.
• In‑depth understanding of hardware architectures, system‑level IC design implementation, and end‑use scenario creation.
• Strong technical background in FPGA prototype emulation and debug.
• Strong technical background in silicon validation, failure analysis, and debug.
• Excellent board‑level debug capabilities in a lab environment: hands‑on troubleshooting skills for digital logic and analog circuit on PCB using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g., Synopsys Identify, Xilinx Chipscope, Altera Signal scope, Lattice Reveal).
• Design with RTL coding in Verilog and VHDL required.
• Experience using simulation (Model Sim) and synthesis (Synplicity) tools.
• Good knowledge of validating system‑level designs based on embedded processors and peripherals such as SPI, I2C, UART, Ethernet, PCI and USB.
• Familiarity with bring‑up and on‑board debug of 32
  
  Gbps SERDES.
• Hands‑on systems‑level design and debug experience with high‑speed serial communications protocols (mandatory: PHY, PCS and data‑link layer of the OSI protocol stack; desirable: transaction and upper layers).
• Experience with lab equipment:
  Spirent Test Center or equivalent traffic generators and checkers.
• Strong commitment to quality and customer satisfaction.
• Excellent verbal and written communication skills in English.
• Ability to travel 0‑2 times annually if required.
• Skills in C, C++ or object‑oriented programming required.
• Embedded firmware development experience.
• Knowledge of JTAG, SVF and 1532 standards and STAPL programming desirable.
• Experience with Python/PERL/TCL scripting.

• Familiarity with high‑speed SERDES controllers using 32
  
  Gbps PCS, PMA:
  Ethernet 1–400 Gbps, (U)
  S(X)
  GMII, Interlaken, OTN OTUx, SONET/SDH, (E,X,XGS,NG)-PON, 100G‑EPON.
• Experience with video interfaces: SDI‑SD/HD/3
  
  GHD, SDI (5.94, 11.88 Gbps), Display Port (6.48–25.92 Gbps), HDMI (3.96–42.66 Gbps).
• JESD
  204C experience.
• Design and debug experience for additional high‑speed protocols:
  Hybrid Memory Cube, CPRI Rate 1–10+, Serial Rapid IO 4.1, USB 3.0, SATA I–III, Fiber Channel, Coa Xpress.

• Documentation – 15%

• 50 % work in front of computer.
• 50…