Tech Lead Design Engineer - RTL & Silicon Architect
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-09-09
Listing for:
Astera Labs
Full Time
position Listed on 2026-09-09
Job specializations:
-
Engineering
Hardware Engineer, Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
Astera Labs in San Jose is seeking a Tech Lead Design Engineer to architect and deliver the connectivity silicon powering AI clusters. You will own RTL design for blocks from microarchitecture through tapeout and work at the cutting edge of PCIe, CXL, Ethernet, and UALink technologies.
This high-impact role partners with architecture, verification, DFT and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap.
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