Senior FPGA Timing Engineer — STA & Automation
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-09-09
Listing for:
191 Altera Corporation
Full Time
position Listed on 2026-09-09
Job specializations:
-
Engineering
Hardware Engineer, Electronics Engineer, Systems Engineer
Job Description & How to Apply Below
Altera is seeking a Timing Engineer to join its Physical Design team in San Jose, CA. You will lead timing activities and drive convergence from implementation through sign-off for FPGA subsystems.
The ideal candidate brings 5+ years of ASIC/FPGA timing analysis, strong STA knowledge, and scripting skills (Tcl/Python/Perl). Collaboration with RTL, Architecture, and PD teams is essential.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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