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Emulation and FPGA Prototyping Engineer

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Gsme
Full Time position
Listed on 2026-09-10
Job specializations:
  • Engineering
    Test Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 150000 - 210000 USD Yearly USD 150000.00 210000.00 YEAR
Job Description & How to Apply Below

We are seeking an experienced Emulation and FPGA Prototyping Engineer to work closely with startup customers and help them successfully migrate simulation-based designs into emulation and FPGA prototyping hardware environments. This role requires strong hands‑on experience with RTL design and debug, compilation flows, testbench integration, automation, and regression infrastructure. The ideal candidate is comfortable working directly with customers, solving complex technical issues, and building scalable flows that accelerate pre‑silicon validation and hardware/software bring‑up.

Key Responsibilities

Work directly with startup customers to port simulation-based RTL designs into emulation and FPGA prototyping hardware platforms.

Set up, customize, and maintain compilation flows for emulation and FPGA prototyping environments.

Integrate and configure customer testbench environments for hardware‑assisted verification, acceleration, and prototyping use cases.

Build, automate, and maintain job regression infrastructure to support repeatable compiles, test execution, triage, and reporting.

Debug RTL‑level issues across simulation, emulation, and FPGA prototyping environments, including compile failures, functional mismatches, timing‑related issues, and bring‑up problems.

Collaborate with design, verification, software, and customer engineering teams to identify root causes and drive issues to resolution.

Create and maintain scripts, utilities, and automation frameworks to improve compile turnaround time, regression throughput, and debug efficiency.

Support design bring‑up on emulation and FPGA prototyping platforms, including test execution, waveform/debug data analysis, and iterative design fixes.

Document flows, setup procedures, known issues, and best practices for internal teams and customer users.

Provide technical guidance to customers on emulation and FPGA prototyping methodology, design readiness, and debug strategies.

Qualifications

Required Qualifications

5 or more years of hands‑on experience in emulation, FPGA prototyping, RTL design, design verification, or related pre‑silicon validation roles.

Strong RTL debug skills and the ability to diagnose issues at the Verilog/System Verilog level.

Hands‑on experience with Verilog and System Verilog; basic working knowledge of VHDL.

Comfortable reading, modifying, and debugging basic C code used in test environments, transactors, firmware stubs, or validation flows.

Proficiency with scripting and automation using languages such as Perl, Python, Tcl, shell scripting, or similar tools.

Experience setting up or supporting compile flows, build systems, regression infrastructure, and testbench execution environments.

Familiarity with simulation, emulation, and FPGA prototyping concepts, including compile, bring‑up, runtime execution, and debug workflows.

Ability to work in Linux‑based development environments and use standard engineering tools such as revision control, makefiles, logs, waveform viewers, and issue tracking systems.

Strong analytical, troubleshooting, and communication skills, especially in customer‑facing technical engagements.

Ability to work independently in a fast‑paced startup customer environment while coordinating effectively with internal engineering teams.

Excellent verbal and written communication skills, with the ability to explain complex technical issues clearly to customers, peers, and cross‑functional stakeholders.

Demonstrated ability to collaborate effectively across design, verification, software, field engineering, and customer teams to drive technical closure.

Strong ownership mindset, attention to detail, and ability to manage multiple customer issues, priorities, and deadlines in parallel.

Comfortable working in ambiguous or…

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