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ASIC Design Engineer Graduate; Video Silicon IP

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: ByteDance
Full Time position
Listed on 2026-09-10
Job specializations:
  • Engineering
    Hardware Engineer
Salary/Wage Range or Industry Benchmark: 128000 - 316800 USD Yearly USD 128000.00 316800.00 YEAR
Job Description & How to Apply Below
Position: ASIC Design Engineer Graduate (Video Silicon IP) - 2027 Start

Responsibilities

About the team

Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.

We are looking for talented individuals to join our team. As a graduate, you will get opportunities to pursue bold ideas, tackle complex challenges, and unlock limitless growth.

Successful candidates must be able to commit to an onboarding date by the end of the year. Please state your availability and graduation date clearly in your resume.

Candidates can apply to a maximum of two positions and will be considered for jobs in the order you apply. The application limit is applicable to our Company and its affiliates' jobs globally. Applications will be reviewed on a rolling basis - we encourage you to apply early.

Responsibilities
  • As an ASIC Design Engineer in this Video Silicon IP team, we work closely with architecture, algorithm and verification teams to build high performance and low power video processing IPs. Apply your knowledge of computer architecture and ASIC design to create ASIC design for compressing, processing still images and videos.
Qualifications

Minimum Qualifications

  • Individuals who are completing or have recently completed a Bachelor's degree in Computer Science, Electrical Engineering or a related discipline.
  • Knowledge of Video Codecs.
  • Experience with RTL design (System Verilog) or High level Synthesis (HLS).
  • Experience with UVM methodology, SystemC, or DPI.
  • Good programming skills in Python for task automation.

By submitting an application for this role, you accept and agree to our global applicant privacy policy, which may be accessed here:

Job Information

【For Pay Transparency】Compensation Description (Annually)

The base salary range for this position in the selected city is $128000 - $316800 annually.

Compensation may vary outside of this range depending on a number of factors, including a candidate’s qualifications, skills, competencies and experience, and location. Base pay is one part of the Total Package that is provided to compensate and recognize employees for their work, and this role may be eligible for additional discretionary bonuses/incentives, and restricted stock units.

Benefits may vary depending on the nature of employment and the country work location. Employees have day one access to medical, dental, and vision insurance, a 401(k) savings plan with company match, paid parental leave, short-term and long-term disability coverage, life insurance, wellbeing benefits, among others. Employees also receive 10 paid holidays per year, 10 paid sick days per year and 17 days of Paid Personal Time (prorated upon hire with increasing accruals by tenure).

The Company reserves the right to modify or change these benefits programs at any time, with or without notice.

For Los Angeles County (unincorporated) Candidates:

Qualified applicants with arrest or conviction records will be considered for employment in accordance with all federal, state, and local laws including the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. Our company believes that criminal history may have a direct, adverse and negative relationship on the following job duties, potentially resulting in the withdrawal of the conditional offer of…

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