FPGA Silicon Design Engineer

Job Details

* This position does not provide Altera immigration sponsorship
* Must be authorized to work in the United States without employer-sponsored immigration support for this position and meet all applicable eligibility requirements associated with supporting a U.S. government contract.

At Altera, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of FPGA expertise, our mission is to deliver programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets such as AI, cloud, networking, and edge.

Join Altera as an FPGA Silicon Design Engineer and contribute to the design, verification, implementation, and silicon bring-up of next-generation FPGA devices. In this role, you will develop complex digital logic and RTL while supporting the full ASIC implementation flow, from synthesis through physical design, timing closure, power analysis, and production-ready silicon. You will work closely with architecture, design verification, physical design, software, firmware, and product engineering teams to deliver high-performance, power-efficient, and feature-rich FPGA solutions.

The ideal candidate combines strong digital design expertise with hands‑on experience in backend ASIC physical design flows and a disciplined approach to technical execution.

• Architect, design, and implement complex digital logic for FPGA silicon, including general-purpose logic, specialized blocks, control logic, and interconnects.
• Develop, review, and maintain production-quality RTL using Verilog and/or System Verilog in accordance with design specifications and established coding practices.
• Define and execute comprehensive design verification plans using industry-standard methodologies, including UVM, constrained-random verification, and System Verilog Assertions.
• Execute and support the backend ASIC physical design flow, including synthesis, floor planning, placement, clock-tree synthesis, routing, static timing analysis, timing closure, and power analysis.
• Analyze design quality across performance, power, and area (PPA) objectives and implement optimizations to achieve product-level targets.
• Use industry-standard EDA tools to simulate, synthesize, implement, analyze, and debug design blocks and full-chip integrations.
• Collaborate with architecture, verification, physical design, software, firmware, and product engineering teams to define specifications, resolve design issues, and manage integration dependencies.
• Contribute to silicon bring-up, post-silicon debug, characterization, and root-cause analysis of hardware, RTL, timing, and system-level issues.
• Develop and maintain design specifications, architecture documentation, implementation collateral, verification plans, analysis reports, and technical presentations.
• Participate in design and code reviews, provide actionable technical feedback, and communicate risks, status, and trade-offs to cross-functional stakeholders.
• Use scripting and automation to improve design, verification, implementation, analysis, and regression workflows.

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $149,100 - $213,015 USD

• Minimum Qualifications:
  
  Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, plus 8+ years of industry experience in FPGA or ASIC…