Solution Validation Engineer--FPGA​/SoC

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Join our team to build and validate hardware/software co-design solutions for FPGA-based Systems. The work spans AVB, networking, storage, automotive, aerospace, and emerging AI/ML workloads. You will design high-performance FPGA Solutions and the embedded software that drives them

You have a passion for system architecture, digital & embedded design, and system-level validation. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

• Take a technical role across every phase of the product cycle starting from exploration, architecture, implementation, prototyping, validation, productization, and support, covering architecture, design, and hardware validation of IPs.
• Work with architects, hardware engineers, and firmware engineers to scope new features to be developed.
• RTL Development: Design, verify, and validate high-performance logic in System Verilog/Verilog, focused on the data and control path. You will be working with the latest generation of interfaces such as PCIe (Gen 6/7), LPDDR5/6, HDMI 2.1, DP 2.1, USB
  3.1, UFS 4.0, Image Sensors, MIPI-CPHY etc.
• Embedded System Development: Write firmware and low-level system software for the on-chip ARM Cortex (APU/RPU) or RISC-V soft cores. Build and customize embedded Linux images using Yocto-based Embedded Design Flow, including BSP configuration, device trees & kernel/rootfs tuning, and custom recipe and layer development for board-specific software stacks.
• System-Level Integration: Use the AMD (Xilinx) Vivado and Vitis ecosystems to integrate custom IPs with the Network on Chip (NoC), memory, and other subsystems and bring-up Baremetal/Linux for System Level Bring-up and Validation
• Pre-Si Verification: Run pre-silicon verification and emulation to confirm functional correctness and performance.
• Board Bring-Up & Validation: Support new board bring-up from first power-on through a stable, validated platform. Create System Level Designs to validate clocking, resets, memory and other interfaces using the Vivado and Vitis / EDF Tool Chains. Support the boards team with the bench setup and scripts needed to complete bring-up and board validation
• Post-Si Validation: Run post-silicon validation and debug the interactions between embedded software, hard & soft IPs, and the FPGA fabric.

Core profile: FPGA design, high-speed digital, hardware debug, embedded SW and systems design.

• 8+ years of hands-on FPGA designs.
• Strong System Verilog, Verilog, and/or VHDL, with proven AMD/Xilinx FPGA work and strong Vivado proficiency.
• Deep knowledge of clocking, CDC, multi-clock systems, timing closure, XDC/SDC constraints, and static timing analysis.
• Experience designing high-reliability, low-latency/high-throughput, deterministic, real-time systems.
• Working knowledge of System Verilog test benches.
• Hands-on experience with AMD/Xilinx embedded Linux flows: building and customizing images with Yocto-based Embedded Design Flow (BSPs, device trees, custom recipes/layers).
• Excellent hardware debug skills with ILA, oscilloscopes, and logic analyzers, including custom board bring-up.
• Proven board bring-up and validation experience, taking a new board from power-on, boot and interface bring-up and debugging clocking, reset, and hardware issues on the bench.
• Experience with high-speed interfaces: PCIe, Ethernet, DDR5/6, Ser Des, UFS and others such as SPI, I²C, and UART.
• Strong C/C++ for bare-metal programming on ARM/RISC-V cores. Linux kernel-mode driver knowledge is a strong plus.
• Familiarity with Git, scripted/CI builds, automated regression, linting, and structured FPGA workflows. Comfortable automating in Python, Tcl, Makefiles, and Shell.
• Strong ownership and communication, with a track record of mentoring, running…