ASIC Design Engineer; Video Silicon IP; Multimedia Lab San Jose Regular

Join us as we work together to inspire creativity and enrich life around the globe.

Location:

San Jose

Team:

Technology

Employment Type:

Regular

Job Code:

A100401

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Team Introduction The Video Silicon IP team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.

• As an ASIC Design Engineer in this Video Silicon IP team, we work closely with architecture, algorithm and verification teams to build high performance and low power video processing IPs.
• Apply your knowledge of computer architecture and ASIC design to create ASIC design for compressing, processing still images and videos.
• Develop micro-architectures to meet stringent area, power, and performance (PPA) targets for multi-standard codec cores.
• Collaborate with algorithm teams to translate codec standard specifications and proprietary codec improvements into implementable hardware architectures.
• Design and implement RTL (System Verilog/Verilog) for video codec pipeline stages including intra/inter prediction, transform & quantization, entropy coding (CABAC/ANS), in-loop filters, and etc.
• Drive functional correctness in partnership with the verification team using directed and constrained-random UVM test benches; debug and close RTL coverage metrics.
• Understand synthesis, timing analysis, and CDC/RDC checks; work with physical design on floor plan and timing closure guidance.

• Minimum Qualifications- M.S./Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• Minimum Qualifications- 2 years of ASIC front-end design experience as a primary RTL owner.
• Minimum Qualifications
  - Proficiency in System Verilog RTL design or High level Synthesis (HLS).
• Minimum Qualifications
  - Familiarity with UVM/DPI/C++.
• Minimum Qualifications
  - Solid understanding of VLSI design concepts: pipelining, clock gating, memory architecture, bus interfaces (AXI/APB), and SV assertion basics.
• Minimum Qualifications
  - Scripting proficiency in Python for EDA flow automation.
• Preferred Qualifications
  - Experience with Video Codec (H.265/HEVC, H.266/VVC, AV1, VP9, or H.264/AVC) is a big plus.
• Preferred Qualifications
  - Experience with relevant ISP or machine learning based image/video compression.
• Preferred Qualifications
  - Experience with FPGA prototyping for pre-silicon codec validation.
• Preferred Qualifications
  - Practical experience using LLMs (e.g., Git Hub Copilot, Claude, ChatGPT) to assist RTL design workflows.

Founded in 2012, Byte Dance's mission is to inspire creativity and enrich life. With a suite of more than a dozen products, including Tik Tok, Lemon8, Cap Cut and Pico as well as platforms specific to the China market, including Toutiao, Douyin, and Xigua, Byte Dance has made it easier and more fun for people to connect with, consume, and create content.

Inspiring creativity is at the core of Byte Dance's mission. Our innovative products are built to help people authentically express themselves, discover and connect – and our global, diverse teams make that possible. Together, we create value for our communities, inspire creativity and enrich life - a mission we work towards every day.

As Byte Dancers, we strive to do great things with great people.…