Physical Design Engineer; Place & Route

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs’ portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floor planning, place‑and‑route, timing closure, and physical sign‑off.

You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on‑site and in‑person.

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open‑minded behavior and can‑do attitude. Think and act fast with the customer in mind!

• Hands‑on and thorough knowledge of synthesis, place and route, timing, extraction, EM‑IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of System Verilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full‑chip level.
• Experience in working with IP vendors for both RTL and hard‑macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

• Knowledge of design for test (DFT).
• Familiarity with ECO methodologies and tools.
• Knowledge of LVS/DRC closures.
• Experience with high‑speed SERDES or Ethernet PHY design integration.
• Experience with clock tree synthesis optimization.
• Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is 160,000 USD - 195,000 USD for Staff Level, and 203,000 USD - 230,000 USD for Principal Level. You will also be eligible for equity and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non‑binary people, veterans, parents, and individuals with disabilities.