Principal Design Engineer

About the role

Team Credo is looking for a Principal Design Engineer to join our mission to transform connectivity  this role, you will be responsible for the RTL architecture, design, implementation, and verification of advanced Ser Des PHY Digital Signal Processing (DSP) blocks used in next-generation networking, AI, data center, and high-performance computing products. The ideal candidate possesses strong digital design fundamentals, hands-on RTL development experience, and a good understanding of high-speed Ser Des architecture.

This position will be onsite at our San Jose, CA HQ.

is $180,000 - $250,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.

• Purpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
• People: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
• Possibilities: Our belief shapes what’s next. Our technology powers the most reliable and energy-efficient connections around the world – and our team powers new products and markets that come next.

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of digital design experience.
• 10+ years of block-level/system-level verification experience.
• Proficient in bit-true verification and DPI/PLI verification methodology.
• Strong RTL development skills using System Verilog.
• Experience designing high-speed communication or DSP hardware.
• Solid understanding of fixed-point arithmetic RTL implementation.
• Experience with ASIC development flow (e.g. Lint, CDC/RDC, Synthesis, Timing analysis).
• Familiarity with EDA tools from Synopsys, Cadence, or Siemens.
• Strong debugging and problem-solving skills.

• Experience in designing high-speed (>1GHz) Ser Des chip.
• Experience with low power design techniques, power estimation via post gate level simulation or other power analysis tools.
• Familiarity with Forward Error Correction algorithms, including Reed-Solomon, BCH, LDPC, etc.
• Familiarity with UVM verification methodology.

• Define RTL micro-architecture for digital PHY and Ser Des DSP functions.
• Develop synthesizable RTL for DSP blocks (FFE, DFE, MLSD, adaptive equalization, FEC, etc.).
• Work with system architects and algorithm teams to translate DSP algorithms into RTL.
• Optimize designs for performance, power, area, and latency.
• Verify DSP modules and debug functional issues.
• Support synthesis, timing closure, CDC/RDC analysis, and DFT integration.
• Analyze silicon bring-up data with validation teams to resolve issues.
• Support PHY integration and system-level debugging.

Credo’s mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI.

Our product portfolio includes Zero Flap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, Omni Connect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.

Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, gender identity, sexual orientation, pregnancy, marital status, national origin, ethnicity, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email

180000 - 250000 USD (yearly)