Packaging Engineer

Position Summary

The Staff Packaging Engineer develops and optimizes semiconductor packaging solutions from silicon die through PCB-level integration. This role supports advanced packaging development, structural and thermal analysis, assembly process integration, reliability, qualification, and manufacturing readiness for leading-edge semiconductor products. Working closely with R&D teams, component suppliers, CMs/OSATs and customers, the role supports package development and high-volume manufacturing readiness while driving continuous process improvement.

• Develop and optimize semiconductor packaging solutions from die to PCB integration.
• Support advanced packaging technologies including 2.5D and 3D integration.
• Define package stack-ups, substrates, interconnects, materials, and PCB interface requirements.
• Support engineering builds, qualification activities, and HVM readiness.
• Collaborate with R&D teams, substrate/PCB suppliers, and CMs/OSATs

• Perform structural, thermomechanical, and thermal simulations using FEA tools.
• Analyze package reliability risks including stress, deformation, fatigue, etc.
• Optimize package designs for mechanical robustness, manufacturability, and thermal performance.
• Correlate simulation results with lab data and failure analysis findings.

• Develop and optimize assembly processes including flip-chip, die attach, underfill, molding, singulation, SMT, and PCB-level assembly.
• Provide hands-on support for prototype builds, troubleshooting, and yield improvement.
• Work with suppliers and CMs/OSATs to improve assembly processes and manufacturing readiness.
• Support root cause analysis and corrective actions for assembly and reliability issues.

• Define and execute package qualification plans per JEDEC and relevant standards.
• Support reliability testing and failure analysis activities.
• Support technical discussions related to package integration, manufacturability, and HVM readiness.
• Communicate technical findings and drive continuous process improvements.
• Semiconductor Package Development
• Structural, Thermal & Reliability Analysis
• Assembly Process Optimization & Manufacturing Readiness
• Failure Analysis & Technical Problem Solving
• Cross-Functional Collaboration
• Technical Communication & Influence
• Continuous Improvement & Process Optimization

• Master’s degree in Mechanical Engineering, Electrical Engineering, Materials Science, Physics, or related field.
• 7+ years of experience in semiconductor packaging, assembly engineering, or advanced packaging R&D.
• Experience developing semiconductor packaging solutions from die through PCB assembly.
• Experience with semiconductor assembly processes, manufacturing flows, and engineering builds.
• Hands-on experience with assembly process troubleshooting, yield improvement, and manufacturing readiness.
• Experience with structural and thermomechanical simulation tools such as ANSYS.

• PhD in Mechanical Engineering, Electrical Engineering, Materials Science, Physics, or related engineering discipline.
• Experience with advanced packaging technologies including TSV, fan-out, chiplets, heterogeneous integration, or hybrid bonding.
• Experience working with CMs, OSATs, and high-volume manufacturing environments.
• Familiarity with SI/PI fundamentals, package layout, and EDA tools.

Location:

San Jose, CA

San Jose, CA Range: $150,000 - $195,000

Bonus Target: 10% of annualized base pay

Restricted Stock Units Target (as a % of annualized base pay): 45%

The base compensation is based on the primary work location, as ranges are location-specific. Actual compensation will depend on factors such as skills,…