Physical Design Implementation and Signoff Methodology Lead & Architect

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* Job Description:

**** About Altera
** Altera builds the programmable logic and adaptive computing solutions that power the world's most demanding systems — from data centers and networking infrastructure to automotive, aerospace, and industrial applications. As an independent FPGA leader, we combine decades of silicon expertise with a startup's focus on speed and innovation. Our engineers work at the edge of process technology and design methodology to deliver silicon that customers can trust, on schedule, every time.

** The Opportunity
** We are looking for a
** Physical Design Implementation & Signoff Methodology Lead & Architect
** to own and reinvent the implementation and signoff methodology that underpins every tapeout s is a senior individual-contributor role for an engineer who thinks like an architect: someone who doesn't just close implementation and signoff on a single block, but builds the flows, standards, and quality gates — supercharged with an AI/ML-driven mindset — that let every design team close faster, with higher quality and confidence, across every future product.

You will be the recognized authority on physical design (PD) implementation and signoff — with place-and-route implementation, electromigration and IR-drop (EMIR) analysis, timing signoff, and power signoff as your core domains — and you will architect flows engineered to scale cleanly as Altera takes on more concurrent designs, without sacrificing turnaround time or quality.  This role sits on Altera's senior individual-contributor (IC) technical ladder (Senior Principal Engineer / Principal Engineer).

It is built for deep technical leaders who prefer to lead through expertise, architecture, and influence rather than people management — while still shaping strategy and mentoring the next generation of physical design engineers.  
** Level distinction:
**** Principal Engineer**: owns one signoff domain end-to-end — EMIR, timing, or power — across at least two process nodes, and has deployed that methodology to design teams outside their own.
** Senior Principal Engineer**: owns the implementation and signoff methodology architecture across the product portfolio, and has set methodology strategy across multiple product generations.

** What You'll Own / Responsibilities:**
* ** Implementation & signoff methodology strategy —
** Own the end-to-end physical design implementation and signoff methodology — including place-and-route implementation, electromigration and IR-drop (EMIR) analysis, timing signoff, and power signoff — across Altera's product portfolio.
* ** Flow architecture —
** Define and continuously improve PD implementation and signoff flows and standards, ensuring accuracy, full coverage, and efficient turnaround time for every design team that depends on them.
* ** AI/ML-driven productivity —
** Champion an AI/ML-driven mindset across implementation and signoff: introduce predictive and generative techniques — ML-based timing/power/EMIR prediction, automated debug and fix recommendation, intelligent flow orchestration — that meaningfully improve engineering productivity and quality.
* ** Scalable, efficient closure —
** Architect implementation and signoff flows to scale efficiently across a growing number of concurrent designs, enabling faster and more predictable closure without linear growth in engineering effort.
* ** Technology enablement —
** Partner with process/technology teams, EDA vendors, and design teams to qualify and deploy next-generation implementation, EMIR, timing, and power methodologies for advanced process nodes.
* ** Quality and reliability —
** Establish golden reference flows, signoff criteria, and quality gates that protect silicon reliability and drive first-pass tapeout…