Principal SIPI Architect: Chiplet 5D/3D Packaging
Listed on 2026-10-06
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Engineering
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Design & Architecture
Astera Labs is seeking a Principal Package Signal & Power Integrity Engineer to architect, optimize, and sign off SIPI solutions for next‑gen connectivity products. You will lead SIPI strategy across PCIe, CXL, Ethernet, and die‑to‑die interconnect, partnering with silicon, package design, PCB, and OSAT teams to balance performance, cost, and manufacturability.
You will drive modeling standards, correlation with lab measurements, and co-design frameworks for multi-die systems, while mentoring
Are you ready to take on the Principal SIPI Architect:
Chiplet & 2.5D/3D Packaging role at Astera Labs?
We have an opening for a Principal SIPI Architect:
Chiplet & 2.5D/3D Packaging in San Jose, CA, United States within Engineering.
This role, Principal SIPI Architect:
Chiplet & 2.5D/3D Packaging at Astera Labs, could be your next move.
We would love to welcome a new Principal SIPI Architect:
Chiplet & 2.5D/3D Packaging to our organisation in San Jose, CA, United States.
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