Principal Digital Design Architect AI Connectivity SoCs
Listed on 2026-10-06
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Engineering
Hardware Engineer -
Design & Architecture
Astera Labs seeks a Principal Digital Design Engineer to architect and implement next-gen digital designs for AI connectivity. You will own blocks from micro-architecture to silicon bring-up, driving RTL and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR
5.
This role offers work on cutting-edge AI infrastructure with ownership of critical design challenges in a fast-paced,
This is a genuine position to take on the Principal Digital Design Architect for AI Connectivity SoCs role at Asteralabs.
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Join Asteralabs and contribute to our ongoing work.
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This posting is for the Principal Digital Design Architect for AI Connectivity SoCs role at Asteralabs, based in San Jose, CA, United States.
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