Staff Engineer, FPGA

Location: Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

• RTL Design & Architecture:
  Develop and optimize RTL (System Verilog/Verilog) IPs for CXL Type-2 FPGAs, focusing on the CXL.cache controller, command queues and DMA management.
• Command Queue Management:
  Design high‑speed, cache‑line‑granular command queue interfaces to allow host CPUs to efficiently update device registers and control structures.
• CXL Cache Coherency:
  Implement hardware mechanisms to maintain coherent access between host CPU and FPGA, reducing synchronization latency and software overheads.
• Performance Optimization:
  Optimize RTL to meet strict latency and bandwidth requirements, managing memory access patterns and improving the pipeline for high‑speed operations.
• System Integration & Debug:
  Collaborate with software engineers to integrate with kernel drivers and user‑space libraries. Debug complex RTL‑to‑Host issues in a laboratory environment, using tools like logic analyzers, PCIe protocol analyzers, and CXL emulators.
• Verification:
  Develop System Verilog test benches and simulation models to verify protocol compliance and functional correctness, focusing on high‑speed data processing.

• Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD's with 5+ years of industry experience.
• BS/MS in Electrical Engineering, Computer Engineering, or related field with 3‑5+ years of industry experience in FPGA development, with a strong portfolio in high‑performance digital design (More experienced candidates will also be considered at relevant levels).
• Expertise in System Verilog, Verilog, and RTL design tools such as Xilinx Vivado, Intel Quartus and familiarity with simulation tools such as Questa, Xcelium, or VCS.
• Strong computer architecture, memory coherency, and data structures fundamentals.
• Deep understanding of AMBA (AXI/AXIS), PCIe, CXL.cache protocols and CXL Type‑1/2 devices.
• Prior experience in designing coherent memory systems and control path design for accelerators is a big plus.
• Strong analytical and troubleshooting skills to resolve complex hardware bottlenecks.
• Must be highly motivated with excellent verbal and written communication skills, and ability to thrive in a collaborative, multi‑disciplinary environment.

Base Pay Range: $163,000 - $253,000 USD

Benefits:

• 4+ weeks of paid time off a year, plus holidays and sick leave.
• Medical/Dental/Vision/401k and inclusive rewards plan.
• Fertility care or adoption stipend, medical travel support, and virtual vet care for your fur babies.
• On‑demand apps and free confidential therapy sessions for emotional wellness.
• Onsite café and gym, plus virtual classes to stay fit.
• Charitable giving match and frequent opportunities to get involved in community support.
• Flexible work environment to find the right balance.

Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.

When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long‑term conditions, neurodivergent individuals, or those requiring pregnancy‑related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.

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