Senior Static Timing Analysis Methodology Lead Engineer​/Technical Lead

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Job Description:

About Altera At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role You will be working in Design Automation group for the technical owner of Static Timing Analysis flows and timing modeling methodology across Altera's ASIC, Custom and Semi-Custom IP designs — and the leader of the small team that delivers it.

Responsibilities Real architectural latitude. We are in the middle of a genuine modernization: standing up next‑generation characterization flows, and onboarding timing sign‑off into a new unified flow environment. There is meaningful greenfield work here, not just incremental maintenance. Breadth you rarely get in one seat. Block‑level, full‑chip, transistor‑level and FPGA timing collateral all live in this domain. Few timing DA roles anywhere span SPICE‑level circuit simulation and cell characterization at one end through customer‑facing FPGA timing deliverable flows at the other.

A seat at both tables. You will represent the timing DA domain with design team leads, physical design, technology enablement and QRE partners in cross‑functional methodology forums and working groups, and you will drive our engagements with the major EDA vendors — evaluating capabilities, escalating what blocks us, and shaping roadmaps. Being the bridge between what our designers need and what the tools can actually do is the heart of this role.

It reports directly to the DA engineering director for the domain, so your technical judgment carries without layers of translation. Real production flows, real users. This is a hands‑on CAD role: you will develop and release production‑grade flows, regressions and automation, then support the design teams running them — triaging tickets, debugging timing issues alongside designers on live tape‑outs, and delivering the training and documentation that make the methodology stick.

The best ideas in this domain come from sitting with the people closing timing under schedule pressure. Colleagues whose expertise reaches well beyond STA. You will work alongside a small group of deep specialists whose domains span circuit simulation and optimization, custom cell characterization and Liberty model generation, FPGA timing model generation, and timing derate and reliability methodology. Being the technical lead here means influencing the whole chain from transistor‑level simulation through characterization to the timing models our design teams and our FPGA software toolchain ship — not just the analysis step in the middle.

If you have ever wanted your timing decisions to reach all the way back into how the models are built, this is that seat. Room to grow your own technical range. You will set technical direction and mentor engineers on timing methodology, and you should expect to learn as much from the characterization and circuit‑simulation depth around you as you bring to it.

You will also have a genuine voice in how we invest in the timing domain going forward. AI where it actually pays off. We are actively applying AI and ML inside our design automation flows — runtime and resource prediction, corner reduction, knowledge capture from debug. If you want to bring those techniques into timing,…