Physical Design Technical Lead

About Altera

Altera is the world’s largest pure‑play FPGA solutions provider, with four decades of FPGA expertise. Our mission is to deliver programmable technologies that help customers innovate and scale across AI, cloud, networking, automotive, and edge computing.

We are looking for a Physical Design Technical Lead to own complex SOC and block‑level implementation challenges end‑to‑end. The role encompasses floor planning, power intent, synthesis, place‑and‑route, clock tree synthesis, ECO closure, and final sign‑off. It also involves shaping future ML/AI‑driven implementation flows and mentoring a small team of physical design engineers.

• Own floorplan architecture and power domain partitioning for large, multi‑million‑instance SOC designs.
• Drive block‑level implementation through synthesis, place‑and‑route, CTS, and ECO closure with sign‑off quality results.
• Lead cross‑functional convergence on timing, power, and area targets across multiple concurrent tape‑out projects.
• Collaborate with RTL, DFT, packaging, and analog teams to resolve integration challenges proactively.
• Define and enforce physical design guidelines, constraint authoring (SDC/UPF), and methodology standards.
• Achieve full signoff closure: STA (multi‑corner, multi‑mode), IR drop, electromigration, DRC/LVS, antenna.
• Drive PPA optimization strategies, including innovative floor planning, clock topology, and routing resource planning.
• Lead critical‑path analysis and timing‑driven ECO resolution with design and library teams.
• Manage hierarchy and partitioning trade‑offs for hierarchical versus flat implementation flows.
• Champion the integration of ML/AI‑based optimization engines into production PnR flows.
• EVALUATE and productize emerging AI tools from EDA vendors and internal research.
• Develop and maintain feedback loops between signoff results and ML training data pipelines.
• Partner with CAD and automation teams to deploy AI‑driven ECO, congestion prediction, and closure acceleration scripts.
• Present findings and flow enhancements at internal design reviews and external EDA forums.
• Mentor a team of 3–8 physical design engineers across multiple project tracks.
• Lead design reviews, closure reviews, and retrospectives to drive continuous improvement.
• Represent Physical Design in architecture planning meetings and influence design‑for‑implementability decisions.
• Contribute to internal white papers, methodology documentation, and IP reuse initiatives.

• Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of progressive experience in physical design or SoC backend for advanced semiconductor products.
• 4+ years in a technical lead, senior lead, or principal-level physical design role with ownership of complex physical design execution.
• At least 3 successful tape‑outs with direct hands‑on ownership at advanced process nodes (7nm or below).
• 5+ years of SoC‑level floor planning, top‑level integration, and full‑chip physical implementation experience.
• 10+ years of hands‑on experience with Synopsys Fusion Compiler and/or Cadence Innovus.
• 8+ years of static timing analysis and closure using Synopsys Prime Time (including MMMC, SI/crosstalk, and path‑based analysis).
• 5+ years of power integrity analysis and sign‑off using Ansys Red Hawk or Cadence Voltus.
• 5+ years of multi‑voltage and low‑power design methodologies (UPF/CPF, MTCMOS, retention, isolation).
• 5+ years of physical verification and sign‑off flows using Mentor Calibre DRC/LVS, with exposure to Cadence PVS.
• 8+ years of scripting and automation in Tcl, and 3+ years in Python, Perl, or similar languages.
• 2+ years experience evaluating ML/AI‑driven physical design tools or methodologies.
• 2+ years experience applying custom ML/AI‑based workflows for timing prediction, hotspot detection, congestion modelling, or PPA optimization.
• 2+ years interpreting ML model outputs and translating them into actionable design decisions.
• 2+ years working with Python‑based data pipelines for design metric collection, analysis, or visualization.

• Experience with FPGA or structured‑ASIC fabric…