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HBM Logic Architect

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: SK hynix America
Full Time position
Listed on 2026-09-10
Job specializations:
  • IT/Tech
    Hardware Engineer, Systems Engineer
  • Engineering
    Hardware Engineer, Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 150000 - 260000 USD Yearly USD 150000.00 260000.00 YEAR
Job Description & How to Apply Below

About SK hynix America

At SK hynix America, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

Job Title:

HBM Logic Architect Office

Location:

San Jose, CA Job Type: Full-Time Work Model:
Onsite About SK hynix America

At SK hynix America, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We’re looking for innovative minds to join our mission of shaping the future of technology. At SK hynix America, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we’re driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices.

As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

Job Summary:

This role involves establishing close technical engagement with key US-based customers to address immediate base-die architectural challenges in HBM and 3D-stacked DRAM. You will be responsible for building a compact and focused HBM Architect Design team in the US to directly support these critical customer interactions. The position also requires developing advanced and customized HBM architectures for future products while strengthening competitiveness through sustained collaboration and technical leadership.

Responsibilities:
  • Define, design, and validate digital IP for ASIC/SoC products.
  • Perform RTL design and implementation based on approved specifications.
  • Collaborate with cross-functional teams to define IP functionality, behavior, and architecture.
  • Review digital IP requirements and evaluate architecture options based on PPA targets.
  • Determine or contribute to architecture decisions for digital IP implementation.
  • Develop and verify RTL designs using industry-standard design methodologies.
  • Provide design guidance and support for physical design implementation.
  • Strengthen digital IP design capabilities for HBM and next-generation DRAM development by securing personnel for real-time support near customer sites.
  • Drive system-level co-optimization beyond standalone DRAM design.
  • Build deep technical partnerships with U.S.

    -based customers.
  • Improve competitiveness through close engagement with customers in the U.S.
Qualifications:
  • Bachelor’s degree or higher in Electrical Engineering or a related discipline(Master’s preferred).
  • 5+ years of relevant experience in semiconductor, ASIC/SoC, digital IP, memory, or PHY design.
  • High-speed digital PHY or high-speed IP design and analysis
  • DRAM memory controller design and analysis
  • DRAM DFT/DFD architecture, design, or analysis
  • PHY/TSV bit macro design, TSV PHY hard macro…
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