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Lead Design Engineer - DDR Validation & Insight Automation
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-08-22
Listing for:
Cadence
Full Time
position Listed on 2026-08-22
Job specializations:
-
Quality Assurance - QA/QC
Quality Engineering
Job Description & How to Apply Below
Cadence in San Jose, California is seeking a skilled individual to lead electrical and functional validation for advanced DDR interfaces such as DDR5 and HBM
4. The ideal candidate will create innovative testing strategies, transform data into insights, and drive collaborative debug processes.
The role requires M. Tech + 4 years or
B. Tech with 6 years of experience. The position offers a salary range of $114,800 to $213,200, along with benefits including paid vacation, 401(k), and a variety of medical plans.
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