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Senior Principal C++ Engineer FPGA Timing & QoR

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Cadence Design Systems, Inc.
Full Time position
Listed on 2026-05-31
Job specializations:
  • Software Development
    Software Engineer, Embedded Software Engineer
Salary/Wage Range or Industry Benchmark: 154000 - 286000 USD Yearly USD 154000.00 286000.00 YEAR
Job Description & How to Apply Below
Position: Senior Principal C++ Engineer for FPGA Timing & QoR

Cadence Design Systems, Inc. is seeking an experienced C++ Software Engineer for its Protium Software Development Team in San Jose, California. You will enhance and support FPGA-based prototyping products, focusing on timing flow and algorithm development.

The role requires a BS and 10+ years of experience or an advanced degree with less experience. Salary ranges from $154,000 to $286,000, along with bonuses, equity, and comprehensive benefits.

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Position Requirements
10+ Years work experience
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