Compiler Engineer - PyTorch + Kernel DSLPLATE

Location: Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

• Adapting torch.compile to our backend: lowering Inductor's IR to our hardware, defining what gets fused, what gets specialized, and where the compiler should yield to hand‑written kernels.
• Building or extending kernel DSLs for our hardware: taking a tile‑based programming model (Triton‑style), a higher‑level expression (Helion‑style), or a custom DSL we design, and lowering it to our ISA, our memory hierarchy, and our collective primitives. Where existing DSLs' GPU assumptions break, deciding what to change in the frontend, the IR, or the backend.
• Designing placement and scheduling passes: given a graph and our distributed memory model, deciding where tensors live, when to migrate them, and how to overlap compute with data movement. This is the layer where our hardware's differentiator shows up most directly.
• Implementing parallelism‑aware lowering: making tensor, pipeline, expert, and sequence parallelism first‑class in the compiler IR rather than bolted on at the framework layer.
• Fusion, tiling, and memory planning: the classical compiler problems, reframed for a non‑uniform memory hierarchy where the right tile size and the right placement are coupled decisions.
• Upstream contributions: where we use open‑source DSLs, we want our work to land upstream rather than live in a private fork. You'll engage with upstream review processes for PyTorch, Triton, Helion, and adjacent projects.

• Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD's with 5+ years of industry experience.
• 3‑5+ years of industry experience in at least one of:
  Triton, Helion, MLIR, XLA, TVM, Inductor, IREE, CUTLASS, or a proprietary equivalent (More experienced candidates will also be considered at relevant levels).
• Experience designing a kernel DSL or its IR from scratch, or making non‑trivial language‑level changes to an existing one.
• Experience with MLIR — writing dialects, passes, or backend integration.
• Experience building PyTorch backends for non‑CUDA accelerators (XPU, ROCm, MPS, TPU, custom).
• Experience with kernel autotuning, performance modeling, or cost‑based compilation.
• Background in HPC, distributed systems, or NUMA‑aware programming — anything that built intuition for non‑flat memory.
• Open‑source contributions to PyTorch, Triton, Helion, LLVM/MLIR, or similar projects is a big plus.

The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job‑related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance.

This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.

With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.

You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.

Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.

With on‑demand apps and free confidential therapy sessions, you’ll have support no matter where you are.

Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.

Benefits are best when you have the space to use them. That’s why we facilitate a flexible environment so you can find the right balance for you.

Base Pay Range
$163,000—$253,000 USD

Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all…