Lead Software Engineer

Overview

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is the industry leader of Verification IP (VIP) with products supporting several communication protocols and memory interfaces. Cadence VIP fits into nearly every verification environment with support for all major simulators and verification languages. Our VIP delivers the advanced features that you need to maximize your productivity and keep projects moving forward.

The VIP PCIe R&D team is looking for a self‑motivated, hands‑on, and creative Lead Software Engineer who can be part of the PCIe verification IP team and development efforts of the most complex industry‑leading software solutions for hardware/SOC memory and protocol verification. This industry‑leading and proven technology is critically important for state‑of‑the‑art products that are existing or under development.

• Software development and validation of PCIe Verification IP.
• Participate in development efforts of the PCIe product to meet customer use models, solution requirements, protocol specifications, and execute necessary software development practices to create reusable, robust software solutions that enable verification of interface protocols.
• Collaborate with a multi‑site, diverse team to contribute to PCIe verification IP development, milestones, technical roadmaps, and people training for success.
• Work with technical support lead and key customers to resolve implementation or usage issues, as Cadence VIP products are used within various verification environments and timing‑critical to customers’ successes.

• BS with a minimum of 4 years of experience, OR MS with a minimum of 2 years of experience, OR new PhD graduate.
• Extensive experience modeling in C/C++ and a background in object‑oriented programming, algorithms, and data structures.
• In‑depth understanding of space/time complexity and advanced debugging techniques for proficiency in troubleshooting software issues and debugging a large codebase.
• Strong analytical and problem‑solving skills with the ability to visualize processes and outcomes.
• Outstanding all‑round communication skills and the ability to work collaboratively in a dynamic multi‑location environment.

• Working knowledge of PCI Express (PCIe) protocol or one or more of the following protocols: USB, NVMe, SATA, Display Port, etc.
• Knowledge of Verilog/System Verilog languages and OVM/UVM verification methodologies.
• Experience with digital logic design or IP/SoC level verification flow.
• Customer orientation and knowledge of the EDA tool flow.

The annual salary range for California is $114,800 to $213,200. You may also be eligible for incentive compensation: bonus, equity, and benefits. The salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies, and work location.

Paid vacation and paid holidays; 401(k) plan with employer match; employee stock purchase plan; a variety of medical, dental, and vision plan options; and more.

Cadence is committed to equal employment opportunity throughout all levels of the organization. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.