Firmware Architect

Responsibilities

• Own the end‑to‑end firmware and embedded‑software architecture for TYLsemi chiplets.
• Define the firmware/hardware interface with Chip Architects, MCU subsystem architecture from the firmware perspective, and the chip’s debug interface and features.
• On‑die tasks: boot and secure boot, link sequencing, PCIe/CXL controller configuration and enumeration, address‑translation (NTB/ATT) setup, MSI‑X and AER handling, reset/FLR, power management, telemetry, and in‑field firmware update.
• Host‑side: kernel drivers, device‑virtualization/shim (synthetic PCIe device, VFIO‑mdev class), management libraries/APIs, and IOMMU coordination.
• Define the hardware/software boundary in architecture and RTL, own register maps and UCIe sideband/mailbox protocols.
• Create a unified firmware development and DV test flow with a single source of truth, and drive HW/SW co‑verification.
• Stay hands‑on through first silicon.
• Lead pre‑silicon firmware and host‑software development on emulation and virtual platforms, and post‑silicon bring‑up and debug.
• Build firmware engineering infrastructure: CI, automated and HIL testing, requirement traceability, secure‑development practices, and RAS/error‑handling strategy.
• Define firmware release, quality, and security criteria across products and customers.

• Serve as the technical bridge between firmware/software and architecture, RTL, DV, PHY/IP vendors, and program management.
• Engage directly with customers: compute‑SoC partners on PCIe/CXL enablement and integrators on firmware and management libraries.

• Set technical direction, roadmap, and clear subsystem ownership (boot/security, PCIe/CXL management, host drivers and virtualization, RAS/telemetry).

• BS/MS in Electrical / Computer Engineering or Computer Science.
• 12+ years of embedded firmware development, including at least 5 years of silicon‑level bring‑up and validation of high‑speed interface IPs.
• Working knowledge of DV and HW/SW co‑simulation/co‑verification flows, and the ability to define a unified firmware + DV test flow.
• Expert‑level C and assembly for resource‑constrained embedded CPUs (RISC‑V or Arm Cortex‑M/R class); strong debugging skills with JTAG/OpenOCD, trace, and logic analyzers.
• Hands‑on experience with HPC compute SoC firmware ecosystems—UEFI/BIOS bring‑up, ACPI table authoring, SMBus/I2C/MCTP platform management, VT‑d/IOMMU configuration on HPC platforms.
• Solid understanding of x86 server platform boot flow: PCIe enumeration, ROM interaction, and PCIe error‑recovery paths (AER, DPC).
• Experience with secure‑boot architectures, code‑signing flows, and OTA update mechanisms on embedded targets.
• Comfortable at the hardware‑software boundary: reading RTL, memory‑mapped register specs, and waveforms from simulation or a logic analyzer.

• SPDM implementation experience.
• Familiarity with PLDM for firmware updates and platform telemetry.
• Exposure to chiplet packaging concepts (UCIe, EMIB, CoWoS) and multi‑die power‑sequencing.

150, USD per year (San Jose (HQ)).