Firmware Architect

Firmware Architect

Tyl Semi, Inc. – San Jose, California, United States

About TYLsemi, Inc.

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem:
how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds chiplet infrastructure IP
—the IO, power delivery, and interconnect building blocks—that makes AI/HPC systems actually work at scale.

This isn't a nice‑to‑have. It's the critical path.

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
• Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

• US team: Bay Area preferred, but we hire the best people regardless of location.
• India team: Building a world‑class design center in Bangalore.

We're not a research project. We have paying customers, committed capital, and aggressive timelines. This is a company, not a lifestyle business. We're building to win.

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies s isn't our first rodeo.
• The traction is de‑risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click‑through rate. You're building the silicon infrastructure that powers AI.

READY TO JOIN?

But if you're the kind of person who wants to take the shot, we'd love to talk.

Own the end‑to‑end firmware/embedded‑software architecture for TYLsemi chiplets. Define the firmware/hardware interface together with the Chip Architects for a seamless HW‑to‑SW handoff; define the MCU subsystem (MCU SS) architecture from the firmware point of view; and define the chip's debug interface and debug features.

On‑die: boot and secure boot, link sequencing, PCIe/CXL controller configuration and enumeration, address‑translation (NTB/ATT) setup, MSI‑X and AER handling, reset/FLR, power management, telemetry, and in‑field firmware update.

Host‑side: kernel drivers, the device‑virtualization/transparency shim (synthetic PCIe device, VFIO‑mdev‑class), management libraries/APIs, and IOMMU (VT‑d/SMMU) coordination. Define the hardware/software boundary with architecture and RTL — datapath (credit, ordering, merge/split, address‑translation execution) in RTL; control plane in firmware — and own register maps and UCIe sideband/mailbox protocols. Define a unified flow for firmware development and DV test cases, with a single source of truth shared across firmware and DV (register models, stimulus, and sequences), and drive HW/SW co‑verification.

Stay hands‑on through first silicon.

Drive…