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Sr. Software Engineer - AI Triton Kernels

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: AMD
Full Time position
Listed on 2026-09-09
Job specializations:
  • Software Development
    AI Engineer (Applied/Software), AI Reliability/ Performance Engineer
Salary/Wage Range or Industry Benchmark: 190000 - 270000 USD Yearly USD 190000.00 270000.00 YEAR
Job Description & How to Apply Below

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

The Role

Triton is a widely adopted language and compiler for high-performance GPU kernels, powering major AI frameworks such as PyTorch, vLLM, and SGLang. As AI workloads increasingly rely on Triton-based kernels, first-class Triton support is strategically critical to AMD’s AI software roadmap.

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

The Role

Triton is a widely adopted language and compiler for high-performance GPU kernels, powering major AI frameworks such as PyTorch, vLLM, and SGLang. As AI workloads increasingly rely on Triton-based kernels, first-class Triton support is strategically critical to AMD’s AI software roadmap.

AMD GPUs are an official Triton backend; delivering industry-leading Triton performance on AMD Instinct accelerators is a top priority for AMD. The performance and usability of Triton directly impact the competitiveness of AMD hardware in large-scale AI training and inference.

In this role you will author state-of-the-art performant Triton/Gluon kernels for ML kernels powering the latest and greatest AI models.

You will collaborate with research, compiler, and hardware architecture teams to co-design high-performance solutions, analyze bottlenecks to make AMD GPUs the best-in-class platform for Triton-powered AI workloads.

The Person

The ideal candidate has deep expertise in SIMT programming, parallel algorithms, GPU architecture, and performance engineering. You are comfortable working across the full stack to drive e2e model performance — from vLLM/SGL down to ISA-level performance tuning — and can perform rigorous quantitative analysis to drive measurable improvements.

You thrive in highly technical environments, enjoy solving complex performance problems, and are excited to collaborate across model deployment, compiler, runtime, and hardware teams. Most importantly, you are curious, hands‑on, and willing to learn and work across boundaries.

Key Responsibilities
  • Design, research, implement, and rigorously optimize high-performance matmul, attention (flash, paged, grouped-query), MoE, and fully fused transformer kernels using Triton, targeting large-scale LLM and multimodal workloads
  • Own and product ionize critical Triton/Gluon kernels within vLLM and SGL (e.g., paged attention, extend attention, MoE, quantized kernels, etc), ensuring correctness, scalability, and peak throughput
  • Partner closely with compiler engineers to develop and maintain the Triton AMD backend across ROCm and the LLVM AMDGPU stack, targeting CDNA and next‑generation architectures
  • Drive deep kernel‑level optimizations across the AMD memory hierarchy (LDS, L2, HBM), wavefront execution (wave
    32/wave
    64), vectorization, MFMA utilization, occupancy tuning, and instruction scheduling to maximize hardware efficiency
  • Perfo…
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