Sr. Manager, ATE Test Development Engineer

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.

Achronix is seeking an experienced Senior Manager, Test Development Engineering to lead test program development, characterization, and production test strategies for our FPGA integrated circuits. This role requires deep expertise in Advantest V93000 (93K) ATE, test methodology development, semiconductor process integration, and data-driven yield optimization. The ideal candidate will manage the operations engineering team and work closely with design, product, and DFT teams to define test plans, debug test programs, and improve test efficiency while ensuring cost-effective, high-quality manufacturing.

• Develop, debug, and optimize ATE test programs on the Advantest V93000 (93K) test platform to validate FPGA functionality and performance.
• Utilize off-line tester tools and emulation environments to prepare and validate test flows before deployment on the ATE.
• Utilize efficient vector compression with multi-port vector capability for handling large pattern quantities with large vector depths.
• Own load-board/probe-card design and validation. Ensure test hardware meets performance, reliability, and cost targets.

• Define and execute comprehensive test plans tailored for FPGA architectures in collaboration with design, product, and DFT teams.
• Implement test methodologies to maximize coverage while optimizing cost, yield, and reliability.

• Handle and manipulate industry-standard test pattern formats, including WGL, VCD, EVCD, STIL. In depth understanding of WGL or STIL files and their function.
• Set up and validate functional, ATPG, MBIST, and high-speed loopback tests.
• Understand vector file structures, including cycle-based timing relationships, pin-level sequencing, and event-based triggers.
• Translate simulation patterns into 93K-compatible formats for FPGA functional verification.
• Debug and modify vector files directly on the ATE as needed for test pattern debug and optimization.
• Deep understanding of high-speed memory and serial interfaces such as Ser Des, GDDR, and DDR test's function, purpose, and methodology.
• Utilize efficiently Advantest V93000 (93K) multi-port vectors.
• Commercial pattern conversion tool knowledge.

• Capability of understanding and writing software routines to develop custom test methods to extend ATE’s built-in capabilities to achieve specific test functions such as burning an efuse and digital capture.
• Write C++ based custom solutions for test automation and result analysis.

• Define characterization plans for complex high-power FPGA with the DFT team.
• Analyze process, voltage, and temperature (PVT) variations to assess device performance across environmental and manufacturing conditions, ensuring high-power FPGAs maintain timing, power, and functionality across all specified operating conditions.
• Define production test limits – Use characterization data to establish pass/fail criteria for high-volume manufacturing, preventing yield loss or excessive fallout by setting optimal test limits based on statistical analysis of device behavior.
• Identify performance bottlenecks, timing margin issues, and power-integrity failures through detailed characterization analysis, ATE-to-bench correlation by comparing tester results with bench validation measurements.
• Develop thermal management solution for device under test.

• ATE data processing and transformation – Extract, parse, and structure raw ATE data logs into readable formats such as Excel or SQL databases,…