Synthesis Engineer

As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI’s Photonic Fabric™ is the next‑generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.

The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi‑chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes.

This seamless integration enables XPUs to utilize optical interconnects for both compute‑to‑compute and compute‑to‑memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.

This innovation empowers hyperscalers to enhance the efficiency and cost‑effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO₂ impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier‑1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.

We are seeking a highly skilled and experienced timing and synthesis engineer to join our team. The ideal candidate will have a strong background in timing constraints development, synthesis, front‑end implementation flows & methodologies for both SOC level and block level. They should have experience that includes logic synthesis (MMMC synthesis), logic equivalency checks, STA, timing constraints, functional ECOs, hard IP integration, timing budgeting, optimization, and timing closure of high‑speed designs.

Experience with deep technology nodes such as 5nm/4nm is highly valued.

• Develop and validate timing constraints for intricate SoC designs
• Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for synthesis, PnR and chip timing sign‑off flows
• Own and contribute to various Front‑End Implementation tasks & flows such as synthesis, UPF development, logical equivalence checks (LEC), functional ECOs, etc.
• Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows
• Perform static timing analysis (STA) using industry‑standard tools (e.g., Tempus, Primetime)
• Define and implement synthesis & timing sign‑off methodologies, including process corners, derates, and uncertainties
• Resolve tool issues, independently or working with EDA tool vendors
• Conduct pre‑route timing checks and quality of results (QoR) analysis
• Automate front‑end flows and timing analysis processes using scripting languages such as Tcl or Python
• Create QoR dashboards, histograms for synthesis & STA flows
• Ensure compliance with timing sign‑off checklists and criteria
• Document best practices and lessons learned to drive continuous improvements in future projects

• Bachelor’s degree in electrical or computer engineering (advanced degree preferred)
• Minimum of 5 years of industry experience in ASIC implementation, STA and synthesis
• Strong understanding of ASIC design flows, from RTL to GDSII
• Knowledge and hands‑on experience with synthesis & STA methodologies and implementation
• Proficiency in using synthesis tools, STA tools, and scripting languages (e.g., Tcl, Python)
• Experience with high‑complexity silicon in advanced technology nodes, preferably TSMC N4/N5
• Strong understanding of timing constraint development for hierarchical designs, timing ECO creation and final timing…