Senior ASIC Verification Engineer - UVM​/SystemVerilog Expert

A leading semiconductor company based in Santa Clara, CA is seeking a high-impact MTS Design Verification Engineer. The ideal candidate will have expert-level knowledge in System Verilog and UVM, with strong debugging skills. Responsibilities include developing UVM-based testbench architectures, managing verification plans and collaborating across teams for high-quality deliverables. A Bachelor’s Degree in Electrical/Computer Engineering is required, and candidates with a Master's Degree are preferred.

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