Formal verification Engineer

We are seeking a highly skilled Formal Verification Engineer to define and drive formal strategies that ensure first-pass silicon success. You will own the sign-off approach across complex IP and SoC designs, leveraging advanced formal techniques to tackle the most challenging verification problems.

• Define and execute the formal verification strategy for complex IP and SoC designs.
• Architect robust, scalable FV environments and deploy reusable test benches, methodology flows, and high-coverage SVA assertion suites.
• Collaborate with Architecture and Design teams to translate specifications into comprehensive formal verification test plans.
• Maintain and enhance FV infrastructure, including CI/regression flows and dashboarding, to deliver clear sign-off metrics.
• Apply advanced formal techniques (assume-guarantee, abstractions, reductions) for efficient bug-hunting and debugging.

• Deep, expert-level proficiency with at least one major commercial FV platform (Cadence Jasper Gold, Synopsys VC Formal, Mentor Questa Formal).
• Strong ability to model complex designs in System Verilog and advanced System Verilog Assertions (SVA), including cut-points and environment models for proof convergence.
• Excellent communication skills to influence cross-functional teams and drive technical alignment.

• Experience with NOCs and networking topologies
  , protocols such as AXI/AMBA.
• Understanding of cache coherency principles.
• Background in high-performance design verification