Design Verification Engineer - ASIC​/UVM​/SystemVerilog

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

AMD’s Network Technologies Solutions Group (NTSG) is a leading provider of advanced data center networking technology. Our distributed services platform expands AMD’s data center product portfolio with a high-performance DPU and software stack deployed at scale across major cloud and enterprise environments, including Goldman Sachs, IBM Cloud, Microsoft Azure, and Oracle.

We are seeking a high-impact MTS Design Verification Engineer with strong technical depth, ownership, and the ability to drive verification closure on complex, high-performance ASIC designs.

The ideal candidate brings hands‑on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading verification efforts across IP, subsystem, and SoC levels.

You will work in a fast‑paced, highly collaborative environment and contribute directly to the success of next‑generation AMD networking products.

• Develop robust UVM‑based testbench architectures for IP, subsystem, and SoC level verification.
• Drive test plan creation, feature mapping, and coverage strategy for complex networking and datapath IP.
• Develop high‑quality System Verilog components: stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.

• Own execution of verification plans, regression triage, and debug of architectural, functional, and performance issues.
• Root‑cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet), and system interactions.
• Optimize simulations, coverage closure, and verification signoff methodology.

• Use industry‑standard simulation, debug, and analysis tools (VCS, Verdi/DVE, coverage tools, waveform analysis suites).
• Contribute to verification methodology improvements, automation, and infrastructure enhancements (Python/Tcl/Make).

• Collaborate closely with RTL design, architecture, validation, firmware, and emulation/HAPS teams to ensure high‑quality deliverables.
• Participate in design reviews, microarchitecture definition, and bring a verification perspective into early design stages.
• Mentor junior engineers and provide technical leadership within the verification team.

• Expert‑level knowledge of System Verilog and UVM
• Strong hands‑on experience with System Verilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE)
• Proven experience in verifying complex IP/subsystems with test plans, coverage, and constrained‑random methodologies
• Strong debug skills across architecture, RTL, and testbench layers
• Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar datapath components
• Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure

• Experience with performance verification, power‑aware verification (UPF), or formal verification
• Familiarity with FPGA/HAPS‑based validation and acceleration flows
• Understanding of networking or high‑speed I/O pipelines
• Exposure to architectural modeling or C/C++ reference models

• Strong analytical and problem‑solving abilities with a proven track record of debugging complex issues
• Ability to lead verification tasks independently and drive cross‑team closure
• Excellent verbal and written communication skills
• Comfortable…