Packaging Customer Engineer

Job Overview

Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting‑edge silicon process and packaging technology leadership for the AI era. The IFS Packaging and Test Business Group is a critical revenue enabler and part of Intel’s forward‑looking strategy, focused on developing, growing and executing a robust packaging roadmap.

• Collaborate with IFS Customer product design, internal product design, Silicon process development, Intel's ATTD, and Product Engineering teams to drive product architecture definition, product package design and execution.
• Serve as the engineering interface to IFS Customers for packaging services, promoting Intel packaging technologies, performing technical feasibility and risk assessments, analyzing product ask versus the ATTD packaging roadmap, and closing the deal with the customer.
• Drive customer‑facing technology reviews as the key engineering interface between the Customer and Intel Foundry, owning the customer packaging engineering relationship from product concept through product mass production.
• Work with IFS Business Development, ATTD, ATM and Supply Chain to complete RFQ risk assessments and pricing assessments.
• Capture customer feedback and competitive trends to inform the ATTD packaging roadmap.
• Represent the customer in internal technology working groups for new technologies during path‑finding and development.
• Interact frequently with Intel VPs and Corporate VPs, presenting recommendations and staying conversant with internal roadmaps and external industry trends.
• Operate independently in a highly matrixed structure, presenting to senior management (VP and Corporate VP level).

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field.
• 9+ years of experience in semiconductor packaging.
• Hands‑on experience in one or more of the following areas:
  • Power delivery
  • High‑speed signaling
  • Thermal‑mechanical analysis
  • Process development
  • Die disaggregation architectures
• Experience presenting technical information to external customers and suppliers.

• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM discipline.
• Strong knowledge of Intel packaging technologies.

• Job Type: Experienced Hire
• Shift: Shift 1 (United States of America)
• Primary
  
  Location:
  
  US, Arizona, Phoenix (additional location: US, California, Santa Clara)
• Work Model for this Role: on‑site presence required. Job posting details such as work model, location or time type are subject to change.
• Annual Salary Range (US): $ – $ USD. Pay is determined by location and other factors.
• Internally, a total compensation package includes competitive pay, stock bonuses, and benefit programs covering health, retirement, and vacation.
• Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. Candidates will never be required to pay recruitment or medical examination fees.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

We offer a total compensation package that ranks among the best in the industry, including competitive pay, stock bonuses, and a comprehensive benefits program covering health, retirement, and vacation. To learn more about benefits, visit our benefits page.

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