VLSI Design Verification Engineer

Role description

VLSI Design Verification Engineer

Technical Lead I - VLSI

Who We Are:

Born digital, UST transforms lives through the power of technology. We walk alongside our clients and partners, embedding innovation and agility into everything they do. We help them create transformative experiences and human-centered solutions for a better world.

UST is a mission-driven group of 29,000+ practical problem solvers and creative thinkers in more than 30 countries. Our entrepreneurial teams are empowered to innovate, act nimbly, and create a lasting and sustainable impact for our clients, their customers, and the communities in which we live.

With us, you'll create a boundless impact that transforms your career-and the lives of people across the world.

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You Are:

We are looking for a skilled VLSI Design Verification Engineer to join our engineering team. The ideal candidate will have strong experience in digital design verification, mixed signal verification, and high speed design environments.

The opportunity:

• Develop and execute design verification plans for digital and mixed signal designs

• Build and maintain verification environments using System Verilog

• Define functional coverage space and implement coverage models

• Write and review System Verilog Assertions (SVA) to ensure protocol and design compliance

• Perform high speed interface verification

• Develop and automate verification flows using Python and/or Perl scripts

• Debug functional and performance issues at block, subsystem, and system level

• Collaborate closely with design, architecture, and validation teams

• Review specifications and contribute to verification strategy and methodology improvements

This position description identifies the responsibilities and tasks typically associated with the performance of the position. Other relevant essential functions may be required.

What you need:

• Strong experience in Digital Design Verification and VLSI Design Verification

• Hands on experience with Mixed Signal Verification

• Proficiency in scripting languages such as Python and/or Perl

• Experience in high speed design verification

• Solid understanding of System Verilog verification concepts

• Preferred / Plus Skills

• Experience in defining coverage space and writing functional coverage models

• Expertise in System Verilog Assertions (SVA)

• Familiarity with AMBA protocols:

• APB, AHB, AXI

• Experience verifying serial interface protocols, including:

• SPI, I2C, I3C, UART, MDIO, JTAG

• Educational Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field

• Experience Level

• Typically 8+ years of experience in VLSI design verification (can be tailored for Junior, Senior, or Lead roles)

Compensation can differ depending on factors including but not limited to the specific office location, role, skill set, education, and level of experience. UST provides a reasonable range of compensation for roles that may be hired in various U.S. markets as set forth below.

Role

Location:

California

Compensation Range: $87,000-$131,000

Benefits

Full-time, regular employees accrue a minimum of 10 days of paid vacation per year, receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year), 10 paid holidays, and are eligible for paid bereavement leave and jury duty. They are eligible to participate in the Company's 401(k) Retirement Plan with employer matching. They and their dependents residing in the US are eligible for medical, dental, and vision insurance, as well as the following Company-paid Employee Only benefits: basic life insurance, accidental death and disability insurance, and short- and long-term disability benefits.

Regular employees may purchase additional voluntary short-term disability benefits, and participate in a Health Savings Account (HSA) as well as a Flexible Spending Account (FSA) for healthcare, dependent child care, and/or commuting expenses as allowable under IRS guidelines. Benefits offerings vary in Puerto Rico.

Part-time employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year) and are eligible to…