ASIC Designer Job Santa Clara area,California USA,Engineering

Hello,

Greetings from Libsys Inc...!

We have an opening for the below position and please find JD.

Job Title: ASIC Designer

Location:
Santa Clara, CA (Onsite)

Job Description:

At least 10 years of experience in ASIC/VLSI design
, with a focus on synthesis, design, and DFT.
Strong understanding of digital design principles, and experience with RTL coding in Verilog/System Verilog
.
In-depth knowledge of synthesis methodologies and tools from leading EDA vendors (Genus, Tempus, DC, Prime Time, etc).
Experience with writing design constraints for synthesis, timing closure, gate level simulation, and pipelining at different levels for performance optimization and timing closure.
Experience with DFT flows
, including scan insertion and ATPG.
Familiarity with physical design and backend flow.
Experience with power analysis and optimization flows such as power gating, clock gating, voltage scaling, and dynamic voltage frequency scaling.
Experience with memory BIST and repair, and post-silicon validation.
Experience with deep technology nodes and very large designs.
Experience with scripting languages such as Perl, Python, or Tcl.
Excellent problem-solving skills and ability to work independently and in a team environment.
Strong communication and interpersonal skills, with the ability to interact effectively with cross-functional teams.
Proven track record of delivering successful designs on time and meeting performance, power, and area goals.

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