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Design Verification Engineer
Job in
Santa Clara, Santa Clara County, California, 95054, USA
Listed on 2026-03-03
Listing for:
PACER GROUP
Full Time
position Listed on 2026-03-03
Job specializations:
-
Engineering
Electronics Engineer, Systems Engineer, Test Engineer
Job Description & How to Apply Below
Design Verification Engineer
Job Location:
Santa Clara,CA
Job Duration: 3 Months, Contract to Hire
Job Summary:
- Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.
- Develop test plans and coverage metrics from specifications and writing block and chip-level tests.
- Synopsys/Cadence EDA Verifications tools (Preference:
5) - System Verilog/UVM (Preference:
5)
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