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Junior RTL Design Engineer — AI ASICs

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Upscaleai
Full Time position
Listed on 2026-03-03
Job specializations:
  • Engineering
    Systems Engineer, Engineering Design & Technologists
Salary/Wage Range or Industry Benchmark: 60000 - 80000 USD Yearly USD 60000.00 80000.00 YEAR
Job Description & How to Apply Below
Position: Junior RTL Design Engineer — Grow with AI ASICs
A high-tech company in Santa Clara is seeking an experienced engineer to join their ASIC Design team. The role involves designing micro-architectures, collaborating with cross-functional teams, and ensuring logic design meets specific performance targets. The ideal candidate has at least 2 years of ASIC design experience and a degree in electrical or computer engineering. The compensation range for technical roles is competitive, and a commitment to diversity and inclusion is emphasized.
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