Senior RTL Design Engineer

Location:On-site in Santa Clara, CA
Job Type:Full-Time
Company:Upscale AI
Team Size:+100 employees
Industry:High-Tech / Emerging Infrastructure

You want to be a part of something groundbreaking, where every day you can see the impact of your work. At Upscale AI, you will join a talent-rich group of problem solvers and doers; in a culture that focuses on team, growth, innovation, and creativity. Our goal is to hire and promote an exceptional workforce as diverse as the global populations we serve.

Upscale AI is an equal-opportunity employer committed to diversity, inclusion, and belonging in all aspects of our organization. We know that our individual differences make us better.

As a member of the ASIC Design team, you will work closely with the architecture team and define and document micro-architecture on next generation designs.

• Responsible for the logic design/RTL entry that meets the power, performance, area targets.
• Collaborate closely with design verification and emulation teams to confirm that test plans meet architecture and design intent, debug complex test scenarios and coverage closure
• Work closely with the physical design team on timing closure and area optimization
• Work with the design for test team to integrate DFT headers
• Work independently, communicate effectively and collaborate with cross functional teams
• Mentor junior team members and summer interns and cultivate a growth mindset among the team to encourage collaboration and inclusion.

• BE or MS in EE, CE, CS
• 8+ years of related technical engineering experience.
• 8+ years of industry experience in logic design with a proven record of accomplishment of delivering complex ASICs like networking ASICs, CPUs, GPUs, So Cs
• Experience using System Verilog and SVA
• Hands on experience with front-end design tools like Lint, CDC, RDC
• Analyzing timing, area, power reports and ability to drive design fixes
• Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
• Able to thrive or lead in a fast-paced startup environment.

• 12+ years of relevant industry experience with a proven track record of successful tapeouts
• Scripting proficiency using Python, Perl etc.
• Experience in selecting and integrating complex third party IPs: PCIe, ARM Cores, Security IPs, Ethernet IPs, Ser Des, UCIe etc.
• Experience with hands-on silicon bring-up and debugging complex issues in the lab
• Knowledge of verification principles and coverage closure
• Experience in deploying or debugging failures from formal verification setups
• Past work experience on high performance, low latency networking ASICs is a big plus
• Understanding of buffer management, arbitration and scheduling, crossbars, datapath architecture and design is highly desirable
• Experience with on-chip CPU subsystem is a plus
• Experience collaborating with third party IP vendors

The national pay range for our technical roles is $100,000-$500,000. The national pay range for our non-technical roles is $75,000-$470,000. Individual compensation will be commensurate with the candidate’s experience aligned with Auradine’s internal leveling guidelines and benchmarks.

Upscale AI is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans.

Upscale AI is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at:  This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case‑by‑case basis.