ASIC Front End Flows & Methodologies Engineer

Location:On-site in Santa Clara, CA
Job Type:Full-Time
Company:Upscale AI
Team Size:+100 employees
Industry:High-Tech / Emerging Infrastructure

You want to be a part of something groundbreaking, where every day you can see the impact of your work. At Upscale AI, you will join a talent-rich group of problem solvers and doers; in a culture that focuses on team, growth, innovation, and creativity. Our goal is to hire and promote an exceptional workforce as diverse as the global populations we serve.

Upscale AI is an equal-opportunity employer committed to diversity, inclusion, and belonging in all aspects of our organization. We know that our individual differences make us better.

As a member of the ASIC Front End team, you will work closely with the design, backend and DFT teams on methodology and flow implementation

• Responsible for front end flows and methodologies including synthesis, LEC, LINT, CDC etc.
• Responsible for setting up Make flows that are extendible, re-usable and deployed consistently across the project
• Ability to write and debug timing constraints
• Work independently, communicate effectively and collaborate with cross functional teams

• BE or MS in EE, CE, CS
• 3+ years of industry experience as an ASIC Tools/Flows/Methodologies engineer
• Lead the development and deployment of robust Front-End flows, including Synthesis, Logical Equivalence Checking (LEC), LINT, and Clock Domain Crossing (CDC).
• Architect and maintain scalable, Makefile-based build systems that support multi-user, project-wide execution and consistency.
• Partner with Design and Backend teams to develop, validate, and debug SDC constraints to ensure smooth handoffs to Place & Route.
• Strong scripting skills in TCL/Python/Perl/shell scripting etc.
• Track block level QoR and act as a liaison between design and backend teams to resolve PPA issues
• Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
• Directly interface with EDA vendors (Synopsys/Cadence) to resolve tool bugs and influence future feature sets.

• 5+ years of relevant industry experience with a proven track record of successful tapeouts
• Familiarity with Synopsys Design Compiler
• Familiarity with Cadence Conformal for LECs and ECOs
• Experience with functional ECOs and validating them using LEC tools
• Prior experience with Static Timing Analysis (STA)
• Understanding of Design for Test and ability to do basic debug of RTL level DFT insertion flows
• Growth mindset and enthusiasm to learn and grow in a fast paced start-up environment

The national pay range for our technical roles is $100,000-$500,000. The national pay range for our non-technical roles is $75,000-$470,000. Individual compensation will be commensurate with the candidate’s experience aligned with Auradine’s internal leveling guidelines and benchmarks.

Upscale AI is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans.

Upscale AI is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at:  This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.