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Design Verification Engineer
Job in
Santa Clara, Santa Clara County, California, 95054, USA
Listed on 2026-03-04
Listing for:
PACER GROUP
Full Time
position Listed on 2026-03-04
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
Design Verification Engineer
Job Location:
Santa Clara, CA
Job Duration: 3 Months, Contract to Hire
Job Responsibilities:
- Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.
- Develop test plans and coverage metrics from specifications and writing block and chip-level tests.
- Create PERL/Python scripts to automate creating verification environments, tests generation and debugging.
- Failure analysis of Register Transfer Level and Gate simulations and resolve them by working with design engineers.
- Create low power testcases using UPF or CPF to verify the desired power intent of the SoC.
- Work with architects to determine the use-case scenarios to simulate
- Synopsys/Cadence EDA Verifications tools (Preference:
5) - System Verilog/UVM (Preference:
5) - Python (Preference:
3)
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